Lecture 5 on RC delay - logical effort 2015

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This is the lecture about RC delay and logical effort.

Note that there is an error around 12.52. For the re-sized 2+1 And-Or-Invert gate the resulting logical efforts are not all the same:

For inputs A and B we get 2, as stated in the video, but for the C input the logical effort becomes 5/3 since the nMOSFET was decreased from 2 to 1.