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In this video we explain how to lay out a CMOS circuit in the standard-cell style
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I forgot to turn on the recording at the end of the lecture, so here are the solution to Quiz 2. And then I also included the fanout-of-4 problem.
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Lecture on dynamic properties of CMOS inverter. Definition of effective resistance during switching. Inverter two-port model. Definition tau, the FO1 delay of an ideal inverter without parasitic…
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This is lecture 2 about the MOS field-effect transistor from 2015
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Lecture 3a is about CMOS inverter and its static characteristics
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This is the lecture about RC delay and logical effort. Note that there is an error around 12.52. For the re-sized 2+1 And-Or-Invert gate the resulting logical efforts are not all the same:For inputs…
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